1. Technical Field
The invention relates generally to computer systems with dynamic buses and, more specifically, to a dynamic bus in a computer system with a singular central precharge device.
2. Background Art
One method of writing data to a dynamic bus entails using precharge devices. Precharge devices pull the bus to a logical high or logical low after each data write to charge the bus to a known state before the next data write occurs. In order to accommodate both the data write and the precharging of the buses, the precharge of the prior art bus would be done in one phase of the clock cycle (e.g., the clock high cycle), and the data write, controlled by a delayed output enable (OE) signal, would occur during the other phase of the clock signal (e.g., the clock low cycle). The delaying of the OE signal by a predetermined number of clock cycles ensured that the bus would be precharged before a data write.
U.S. Pat. No. 4,849,658, "Dynamic Logic Circuit Including Bipolar Transistors and Field-Effect Transistors," (issued July 1989 to Iwamura et al. and assigned to Hitachi, Ltd.) discloses a dynamic bus with a precharge cycle, in which the precharging of the bus is done on the clock low cycle and the data is written to the bus on the clock high cycle. The OE signal is delayed so that the precharging of the bus and data write to the bus does not occur simultaneously.
Because the precharge cycle of the prior art requires the complete first phase of the clock cycle (i.e., during the clock low cycle), the OE signal has to wait until the second phase of the clock cycle to issue. Consequently, delaying the OE signal delays the system and thus degrades system performance.
Examples of other dynamic buses and systems with precharge or refresh cycles may be found in the following United States Patents, which are hereby incorporated by reference: U.S. Pat. No. 5,339,448, "Microprocessor With Improved Internal Transmission," (issued August 1994 to Tanaka et al. and assigned to Hitachi, Ltd.); and U.S. Pat. No. 4,956,820, "Arbiter Circuit for Establishing Priority Control of Read, Write, and Refresh Operations With Respect to Memory Array," (issued September 1990 to Hashimoto and assigned to Texas Instruments Inc.).
Although the aforementioned patents provide a way to precharge/refresh systems, all precharging and OE signal issuing is done on a clock edge. The prior art does not disclose a way of precharging with a singular central device that allows the precharge to take place anywhere in the clock cycle. Accordingly, a need has developed in the art for a dynamic bus system that will allow the precharge to take place anywhere in the clock cycle and will issue the OE signal in the same clock cycle as the precharge signal to improve system performance.